Experience with industry standard verification tools;Prior experience in pre/post silicon validation would be an added advantage;Exceptional candidates with lesser experience (8+ years) shall be considered;BE/B.Tech/ME/M.Tech…Read more

Experience with industry standard front end tools such as Synopsys VCS/Spyglass/DC/PT,;Prior experience in pre/post silicon validation would be an added advantage;verification engineer, with a large portion…Read more

Prior experience in pre/post silicon validation would be an added advantage;Exceptional candidates with lesser experience (7+ years) shall be considered;Knowledge of Verilog and/or VHDL, and experience…Read more

complexity and should be able to deliver high quality designs efficiently;Circuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies;Exceptional candidates with lesser…Read more

Digital Verification team is working on IP verification and SoC verification projects for our various tier 1 &;Experience of working with teams across geographies and managing project team;3 to 12…Read more

Experience : 3 to 12 years;Experience in Digital module micro-architecture and design;Good knowledge of Synthesis, STA and DFT aware design;Experience in basic RTL simulationRead more

We serve the Tier 1 customers in the semiconductor space;Experience : 3 to 12 years;* Hands on experience on the entire PD Flow from Netlist to GDSII;Candidate is expected to have expertise in either Cadence…Read more

Circuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies;Experience : 2 to 6 years;Experience 2-6 Years experience in analog design,;o High speed Memory interfaces…Read more

This role requires team managing experience;Experience : 7 to 10 years;Primary and hands on experience in Analog and IO Circuit Design;Stake holder management experience (client facing, interaction and…Read more

Experience : 3 to 10 years;Primary and hands on experience in Analog and IO Circuit Design;3) Well versed with Liberty , IBIS , Verilog View generationRead more

doing various required physical verifications;3-5 years of experience in AMS/RF layout-design;Experience : 2 to 10 years;Preferred experience in modules like PLL, Data-Converters & PMIC blocks;Preferred…Read more

Good Understanding of the views like lef;Good debugging and problem solving skills;Should be well versed with standard EDA tools used for layout editors /RC-extraction, SPICE;Experience : 2 to 8 years;Design…Read more

Team also has experience in developing flash memories;- Experience in running char and debugging issues through liberate;Team with strong experience in development of low power, high performance, high…Read more

Design experience with deep sub-micron process;Team also has experience in developing flash memories;Good Understanding of the views like lef, NLDM, CCS libs etc;Good debugging and problem solving skills;Team…Read more

Good understanding and hands on experience using verification tools (Calibre) for;Team also has experience in developing flash memories;Good experience in leaf cell/block level layouts;Good experience…Read more