Development of the standard cell library from scratch and support of existing libraries
Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment.
Characterization and views generation of the libraries with several custom PVT corners.
Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools.
Maintain accurate and thorough documentation of work, design flows and reports.
Automation of manual tasks to reduce the overall time and effort spent.
Complete ownership of entire development process, mentor and enhance the skill set of junior team members
Experience in the field of Standard cell design, characterization, modelling and QA.
Experience in advanced technology nodes, 28nm and below.
Should be well versed with standard EDA tools used for RC-extraction, SPICE simulators and schematic/layout editors.
Good Understanding of the views like lef, NLDM, CCS etc. .libs is a must.
Understanding issues related to advanced nanometer technologies, IR, electro migration, SI, LOD, Proximity-effects etc is a must.
Good debugging and problem solving skills.
Scripting skills in csh, perl or tcl is an added advantage.
Should be a good team player.
Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: Engineering Design, R&D
Role Category: Engineering Design
Role: Design Engineer
Employment Type: Permanent Job, Full Time