(1-2 out of 2)
RTL Design Engineer 03 Nov

3 - 6 yrs. Bengaluru

Hands-on in Verilog/ VHDL Hands-on in Perl/ Unix scripting Hands on in SoC level RTL integration Han...view more

Standard Cell Characterization 03 Nov

2 - 5 yrs. Bengaluru, Hubli

Development of the standard cell library from scratch and support of existing libraries Circuit de...view more

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